1. Field of the Invention
This invention relates to techniques for reducing parasitic capacitance in integrated circuits, and more particularly to a method of reducing parasitic bit line capacitance in a semiconductor memory circuit as influenced by capacitive coupling between a diffused bit line and overlying conductors.
2. Description of the Prior Art
U.S. Pat. Nos. 3,811,076 to W. M. Smith, Jr., issued May 14, 1974, and 3,841,926 to R. R. Garnache et al, issued Oct. 15, 1974, relate to a process and device structure for fabricating dynamic MOSFET memory cells including the use of a doped-oxide diffusion source and a conductive polysilicon field shield. U.S. Pat. No. 3,841,926 describes the structure for an array of single transistor/capacitor memory cells, as described in U.S. Pat. No. 3,387,286 to R. H. Dennard, which includes a polysilicon field shield spaced from an underlying diffused bit line by relatively thin dielectric layer of silicon dioxide and silicon nitride which also forms the gate dielectric of the transistor. Efforts to provide high density memory chips require that a minimum memory cell size be designed which is compatible with the minimum useful signal strength capable of being reliably detected by sensing circuitry. Detectable signal strength is a function of the size of the storage capacitor, applied voltages and the capacitance of the bit sense lines. In the design of such memory arrays the ratio of the effective capacitance of a bit sense line to that of a single storage cell, referred to as the transfer ratio, has a significant influence on the performance of the memory. Although it is preferable to have a low transfer ratio, it is difficult to reduce the capacitance of the bit sense line effectively. In designs using a diffused bit line, parasitic capacitance includes the junction capacitance of the bit sense line and the capacitance between the diffused line and adjacent insulated conductive electrodes. Various techniques have been previously proposed to reduce the bit sense line to conductive lead capacitance ratio. One technique retains the relatively thick doped oxide over bit line diffusions which effectively reduces the capacitance by increasing the distance between the capacitor plates. Another method of controlling undesired capacitance is to carefully control the etch bias characteristics of the doped oxide diffusion source to reduce the area of overlap capacitance along the edges of the bit diffusion, as described in U.S. Pat. No. 3,975,220. The last mentioned technique has limitations in that the same capacitance characteristics are created for all diffusions on the chip and the effective reduction in capacitance near the junction edges is only a small percentage of the total capacitance of the diffused region. Other capacitance reduction techniques include selectively exposing the portions of the conductors overlying diffusions and thermally oxidizing the conductor (see IBM Technical Disclosure Bulletin, June 1974, page 18), or providing a non-conductive intrinsic polysilicon layer which is rendered conductive only in selective areas by adding conductivity type impurities to those regions desired to be conductive (see IBM Technical Disclosure Bulletin, June 1974, page 17). Such techniques are not preferred because they add the requirement of another mask and alignment step to an already mask alignment sensitive process. What is required is a mask alignment insensitive technique for eliminating the presence of large areas of conductive material passing over the diffused bit lines. Such a process is provided by the invention herein described in which raised portions of a conductive layer are selectively removable by a technique easily adaptable to a manufacturing environment.
Additional related prior art includes the IBM Technical Disclosure Bulletin articles to R. R. Garnache and to O. S. Spencer found in the December 1976 issue, at pages 2471-2, and the April 1978 issue, at pages 4842-3. Both of these references teach the use of a self-leveling photoresist in conjunction with an ion implantation technique which by providing various levels of doping in an irregular surface layer causes different etching rates to be present in the layer after the photoresist is removed such that a somewhat selective or differential etching process removes higher, more heavily doped, regions of the layer at a faster rate than lower, lighter doped, regions. Etching techniques in which a layer of a single material having two different etching rates is etched without the presence of a substantially non-etchable mask are not preferred in semiconductor manufacturing because the end point of the etching step is somewhat arbitrary and therefore difficult to detect.
In addition, various other surface layer etching techniques have been previously described, each has limitations when applied to a manufacturing process which is sensitive to the introduction of additional mask aligning and processing steps, particularly when their implementation requires different materials or operations not already a part of the manufacturing process. For example, U.S. Pat. No. 3,976,524 to B. C. Feng, issued Aug. 24, 1976, teaches a planarization process which requires the use of a patterned photoresist which is required to be flowable after patterning in order to effectively mask regions of an irregular surface not to be removed. U.S. Pat. No. 4,070,501 to V. R. Corbin et al, issued Jan. 24, 1978, is also of interest as it teaches a method for etching via holes in dielectric layers which relies on a surface irregularity to define an aperture in a first light insensitive layer of polymer which has been previously etched to expose only higher portions of the irregular surface.